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| Description: |
Uploaded source code features single codec(One SDO and SDI lines), single stream version of Azalia controller. Here single stream implies one stream packet which can accommodate N channels from one codec of various lengths of samples. For timing interrupt and memory map of working FPGA ram please see accompanying word document. |
| SHA1 Checksum: |
a039a47f5a6967a920bf413967c4a914ec6db372
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