Research
DESIGN:
Each cup will be controlled by a PIC18F26K80. The PIC18F26K80 features the following 1:
- Contains 64 KB Flash Program Memory
- Contains 3.6 KB SRAM
- Runs on 3.8uA
- Idles on 0.880uA
- Operates with -0.3V to 7.5V
The PIC18F26K80 includes many useful peripheral modules:
- Four Capture/Compare/PWM (CCP) modules
- One Master Synchronous Serial Port (MSSP) modules featuring 3-wire SPI (all 4 modes)Two Enhanced USART Modules
- Five individual timer modules
- High-Low Voltage Detect (HLVD) Module
- ECAN Bus Module
The PIC18F26K80 is being implemented in the cup(s) instead of the PIC18F2713 almost entirely for the use of the ECAN Bus Module. The ECAN enables CAN communication without the need for an external CAN Control component. The ECAN features the following:
- Conforms to CAN 2.0B Active Specification
- Message Bit Rates up to 1 Mbps
- DeviceNet™ Data Byte Filter Support
- Six Programmable Receive/Transmit Buffers
- Three Dedicated Transmit Buffers with Prioritization
- Two Dedicated Receive Buffers
- 16 Full, 29-Bit Acceptance Filters with Dynamic Association
- Three Full, 29-Bit Acceptance Masks
- Automatic Remote Frame Handling
- Advanced Error Management Feature
IMPLEMENTATION:
1. One CCP module will be used (on pin 26) to send a PWM signal to the IR LED driver $.
2. HLVD module will be used (on pin 7) to detect a voltage change caused by the PWM signal (to count the cycles) $$.
3. One USART module will be used (with pins 18, 17) to communicate with the RFID reader.
4. One MSSP module will be used (with pins 16, 15, 14) to communicate with the LED driver.
5. ECAN Module will be used (with pins 23, 24) to communicate with the HIU. 6. 3 digital I/O pins (2, 3, 4) will be used to control the state of the audio driver.
This implementation can be seen below.
On the cup, the timers will be used as follows:
1. One timer (timer1) will be dedicated to timing the frame duration for the MIRP transmission and will trigger an overflow interrupt (Each MIRP packet will transmit a 4 frame signal at 150 cycles per frame at 56 kHz. Each frame will be about 2.7ms in duration $$$).
2. One timer will be dedicated to timing the 5 second delay (countdown before sending deadly IR packets) and 2 second delay (between each deadly IR packet). These timing functions do not occur simultaneously.
3. The remaining three timers will be used to control audio and visual effects. Five timers will accommodate multiple simultaneous effects.
ALTERNATIVE DESIGN:
Apart from the PIC series, the MSP430F5XXX family of microcontrollers may also be considered. The MSP430F5XXX features 2:
- 128 – 256 KB Program Memory
- 16 KB SRAM
- Runs on 150uA -290uA
- Idles on 1.5uA – 2.1uA
We did not choose the MSP430F5XXX because it consumes too much power and provides way more functionality than what we need.
- $ The default 8 MHz clock can produce a 55.94 kHz signal.
- $$ Alternatively, a CCP module on capture mode can count the falling edges, or a timer could attempt to count them.
- $$$ The default 8 MHz clock can time this duration with an error of 0.002%. An external crystal can be used to set the internal clock frequency to a multiple 56 kHz. This would allow timer1 to interrupt at exactly the right time (i.e. 150 clock cycle multiples).
Flow chart
References
1. Microchip, “28/40/44/64-Pin, Enhanced Flash Microcontrollers, with ECAN™ and nanoWatt XLP Technology,” PIC18F66K80 Family datasheet, Aug. 2010.
2. Texas Instruments, “MSP430x5xx and MSP430x6xx Family User’s Guide”, Datasheet, Jun. 2008 (Rev. Feb 2013).