This patch adds support for CACHELINE_ALIGNED value for arm
 devices. I hardcode the cacheline size to 32 because this
 value is supported by several arm devices, however a better
 logic needs to be implemented to handle more arm devices.

---
 src/base/basictypes.h |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/base/basictypes.h b/src/base/basictypes.h
index baaa806..db12a26 100644
--- a/src/base/basictypes.h
+++ b/src/base/basictypes.h
@@ -334,6 +334,8 @@ class AssignAttributeStartEnd {
 #if defined(HAVE___ATTRIBUTE__)
 # if (defined(__i386__) || defined(__x86_64__))
 #   define CACHELINE_ALIGNED __attribute__((aligned(64)))
+# elif defined(__arm__)
+#   define CACHELINE_ALIGNED __attribute__((aligned(32)))
 # elif (defined(__PPC__) || defined(__PPC64__))
 #   define CACHELINE_ALIGNED __attribute__((aligned(16)))
 # endif
--