ODIN-II generates more LUTs with adder #46
Labels
bug
Incorrect behaviour
Odin Elaboration
Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase
Odin Tech.Mapping
Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic
Odin
Odin II Logic Synthesis Tool: Unsorted item
Originally reported on Google Code with ID 53
Reported by
JasonH@efinixinc.com
on 2012-12-28 21:58:57- _Attachment: [k4_N1_no_cluster.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-53/comment-0/k4_N1_no_cluster.xml)_ - _Attachment: [k4_N1_no_cluster_rel1_0.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-53/comment-0/k4_N1_no_cluster_rel1_0.xml)_ - _Attachment: [k4_N1_no_cluster_with_adder.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-53/comment-0/k4_N1_no_cluster_with_adder.xml)_
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