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ODIN-II generates more LUTs with adder #46

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kmurray opened this issue Jun 26, 2015 · 1 comment
Open

ODIN-II generates more LUTs with adder #46

kmurray opened this issue Jun 26, 2015 · 1 comment
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bug Incorrect behaviour Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Tech.Mapping Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic Odin Odin II Logic Synthesis Tool: Unsorted item

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@kmurray
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kmurray commented Jun 26, 2015

Originally reported on Google Code with ID 53

What steps will reproduce the problem?

I have attached three xml files with the following run commands:

1. This xml run is directly from the nightly build version# 1342 (Dec.28, 2012).
   Other recent nightly builds have the same issue, described below
   in the "Expected Output" section. 
perl scripts/run_vtr_flow.pl benchmarks/verilog/sha.v arch/timing/k4_N1_no_cluster.xml

2. This run has the xml arch file in 1 above with the adder model added in.
perl scripts/run_vtr_flow.pl benchmarks/verilog/sha.v arch/timing/k4_N1_no_cluster_with_adder.xml

3. With this run, the xml is copied from 1 above, but modified slightly
   to make it run in the previous official release (Feb 2012).
perl scripts/run_vtr_flow.pl benchmarks/verilog/sha.v arch/timing/k4_N1_no_cluster_rel1_0.xml


What is the expected output? What do you see instead?

With the adder inference in the current nightly build, we expect 
the number of LUTs goes down, but instead it goes up by 32% 
(plus the adders) in the case of "sha", compared to the previous 
official release.
Other designs have similar behaviour.

What version of the product are you using? On what operating system?
1. VTR nightly release versions 1294 (Nov 28, 2012) and 1342 (Dec 28, 2012).
2. VTR official release in Feb 2012. 
OS = Ubuntu Linux.

Please provide any additional information below.

Outputs from vpr.out:

1. Run design "sha" with arch/timing/k4_N1_no_cluster.xml in 2012-11-28 nightly build,
I got:
        1 LUTs of size 0
        3 LUTs of size 1
        147 LUTs of size 2
        494 LUTs of size 3
        2459 LUTs of size 4
        38 of type input
        36 of type output
        911 of type latch
        3104 of type names
Total LUT#=3104

2. Run design "sha" with arch/timing/k4_N1_no_cluster.xml plus adder in 2012-11-28
nightly build, I got:
        10 LUTs of size 0
        3 LUTs of size 1
        134 LUTs of size 2
        674 LUTs of size 3
        3073 LUTs of size 4
        38 of type input
        36 of type output
        911 of type latch
        3894 of type names
        329 of type adder
     Total LUT# = 3894 plus 329 adders, 25% more LUTs than without adder (3894 vs 3104);
32% more than Feb 2012 release (3894 vs 2951).

3. Modify k4_N1_no_cluster.xml a bit for Feb 2012 release, the same run I got
       1 LUTs of size 0
       3 LUTs of size 1
       74 LUTs of size 2
       639 LUTs of size 3
       2234 LUTs of size 4
       2951 LUTs in input netlist
       911 FFs in input netlist
    Total LUT# = 2951

Please take a look.
Thanks.
Jianshe 

Reported by JasonH@efinixinc.com on 2012-12-28 21:58:57


- _Attachment: [k4_N1_no_cluster.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-53/comment-0/k4_N1_no_cluster.xml)_ - _Attachment: [k4_N1_no_cluster_rel1_0.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-53/comment-0/k4_N1_no_cluster_rel1_0.xml)_ - _Attachment: [k4_N1_no_cluster_with_adder.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-53/comment-0/k4_N1_no_cluster_with_adder.xml)_
@kmurray
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kmurray commented Jun 26, 2015

Yes, I reproduce the same results for 4-LUTs in the latest version.  This has probably
something to do with technology mapping.  When I map to 6-LUTs, the opposite effect
happens:

Carry-chains: 2001 LUTs
No carry-chains: 2277 LUTs

Reported by JasonKaiLuu on 2013-01-08 19:52:38

@kmurray kmurray self-assigned this Jun 26, 2015
@kmurray kmurray added Odin Odin II Logic Synthesis Tool: Unsorted item bug Incorrect behaviour and removed Type-Defect labels Sep 15, 2016
@kmurray kmurray assigned KennethKent and unassigned kmurray Jan 2, 2017
litghost added a commit to litghost/vtr-verilog-to-routing that referenced this issue May 16, 2019
…modes

Reset illegal_modes prior to attempting cluster routing.
@jeanlego jeanlego added Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Tech.Mapping Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic labels Apr 1, 2020
vaughnbetz pushed a commit that referenced this issue Feb 23, 2023
* cleaned

* make format-py

* write arch cleaned

* yosys -> parmys

* doc update started

* ODIN_II -> odin_ii

* odin_ii refactored
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Labels
bug Incorrect behaviour Odin Elaboration Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase Odin Tech.Mapping Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic Odin Odin II Logic Synthesis Tool: Unsorted item
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