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32-bit RISC softcore for Xilinx FPGAs. Implements most of the MIPS-1 instruction set (all but unaligned load/store); work on coprocessor instruction support is in progress.

I have decided to use this project as the base for my PhD thesis on computer architecture, so effective today (Jul 18 2012) most of my work will be on a private repository. Changes will be svnsynced back to this public repo once my thesis is finished (and possibly periodically during my work).

No commits to the public repo will be accepted until this happens to avoid confusing svnsync.

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