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  ID ▼ Type ▼ Status ▼ Priority ▼ Milestone ▼ Owner ▼   Summary + Labels ▼ Modified ▼ ...
  1 Defect Accepted Critical Mayotte AndreySv...@gmail.com   Abnormally high DC current at +2,5VRAM for U11. Jan 9  
  2 Defect Accepted High Mayotte AndreySv...@gmail.com   Abnormally low voltage +3.0VCC at U28 output. Jan 9  
  3 Defect Accepted High Mayotte AndreySv...@gmail.com   Abnormally low voltage -5V at U19 output. Jan 9  
  4 Defect Accepted High Mayotte AndreySv...@gmail.com   Incorrect footpring for U6. Jan 9  
  5 Defect Accepted High Mayotte AndreySv...@gmail.com   No 26MHz clock signal from U26 in master mode. Jan 9  
  6 Defect Accepted Critical Mayotte AndreySv...@gmail.com   Flash is too small for Spartan 6 LX75 Jan 16  
  7 Defect Accepted High Mayotte plddesig...@gmail.com   TXD1 and RXD1 nets on schema are swapped Jan 11  
  8 Defect Accepted Medium Mayotte c...@close-haul.com   ICAP wishbone interface for Spartan 6 fails to meed timing Feb 9  
  10 Enhancement Accepted High Mayotte AndreySv...@gmail.com   SRAM wiring improvements Jan 16  
  11 Enhancement Discuss Low Mayotte AndreySv...@gmail.com   FT232R wiring enhancement Jan 16  
  12 Defect Accepted Low Mayotte AndreySv...@gmail.com   Schematic error: pin 40 of the LMS is not RX_CLK/2 it's RX_CLK_OUT Jan 16  
  14 Enhancement Discuss Low Mayotte AndreySv...@gmail.com   LMS safe state during startup Jan 18  
  15 Enhancement Accepted Medium Mayotte AndreySv...@gmail.com   SRAM data timing Jan 16  
  16 Enhancement Discuss High Mayotte AndreySv...@gmail.com   Add wideband RX port to one of the LMS Jan 18  
  17 Enhancement Accepted Low Mayotte AndreySv...@gmail.com   Additional choke required to testing current of +1.2VFPGA (core) Jan 17  
  18 Enhancement Discuss Low Mayotte AndreySv...@gmail.com   Replace/remove thru-hole components Jan 25  
  19 Defect Accepted High Mayotte plddesig...@gmail.com   Boundary Scan loading to SPI Flash failed Jan 29  
  20 Defect Accepted High Mayotte AndreySv...@gmail.com   Master/slave switch in slave position completely disables 26MHz Feb 3  
  21 Review Accepted Medium Mayotte plddesig...@gmail.com   Wrong routing of SYS_CLK pin of ET1011C chip Feb 6  
  22 Defect Accepted Medium Mayotte alexander.chemeris   Production image loading doesn't work reliably Feb 8  
  23 Defect Accepted High Mayotte alexander.chemeris   ZPU can talk to one LMS only Feb 6  
  24 Task Accepted Critical Mayotte AndreySv...@gmail.com   LMS chips need cooling Feb 6  
  25 Defect Accepted Critical Mayotte plddesig...@gmail.com   DSP block at FPGA can't be clocked at 13MHz Feb 8  
  26 Defect Accepted High Mayotte AndreySv...@gmail.com   26MHz harmonics at LMS output Feb 19  
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