r-vex - ρ-VEX: A Reconfigurable and Extensible VLIW Processor

Older Nov 18, 2009 issue 10 (Makefile for r-VEX does not work under Ubuntu 9.04) commented on by t.vanas - Yeah, I noticed this as well in Ubuntu (in an earlier version). I believe it's in their dash shell, and it's done to be more POSIX compliant. Using printf would be better for portability. Yeah, I noticed this as well in Ubuntu (in an earlier version). I believe it's in their dash shell, and it's done to be more POSIX compliant. Using printf would be better for portability. Nov 16, 2009 QuickstartGuide Wiki page edited by t.vanas - Revision r45 Edited wiki page through web user interface. Revision r45 Edited wiki page through web user interface. Nov 16, 2009 QuickstartGuide Wiki page edited by t.vanas - Revision r44 Edited wiki page through web user interface. Revision r44 Edited wiki page through web user interface. Nov 12, 2009 issue 10 (Makefile for r-VEX does not work under Ubuntu 9.04) reported by joao.eel - The makefile for synthesis does not work with the Make version that ships with Ubuntu 9.04. The problem is the "-e" flag for the @echo commands. Removing them fixes this problem. This version of Make does not need this flag, the '\' escapes are automatically parsed. The makefile for synthesis does not work with the Make version that ships with Ubuntu 9.04. The problem is the "-e" flag for the @echo commands. Removing them fixes this problem. This version of Make does not need this flag, the '\' escapes are automatically parsed. Aug 05, 2009 r43 (* [r-ASM] Add support for cluster information in assembly fi...) committed by t.vanas - * [r-ASM] Add support for cluster information in assembly files (this information is not used as we currently don't support multi-cluster configurations) * [r-ASM] Add support for cluster information in assembly files (this information is not used as we currently don't support multi-cluster configurations) Aug 05, 2009 OperationsSemantics Wiki page edited by t.vanas - Revision r42 Edited wiki page through web user interface. Revision r42 Edited wiki page through web user interface. Aug 05, 2009 QuickstartGuide Wiki page edited by t.vanas - Revision r41 Edited wiki page through web user interface. Revision r41 Edited wiki page through web user interface. Dec 24, 2008 OperationsSemantics Wiki page edited by t.vanas Dec 24, 2008 QuickstartGuide Wiki page edited by t.vanas Dec 09, 2008 msc_defense_slides.pdf (Slides from Thijs' MSc defense about ρ-VEX) file uploaded by t.vanas - Labels: Featured Type-Docs Labels: Featured Type-Docs Dec 09, 2008 r-vex_icfpt08_poster.pdf (Poster about ρ-VEX as presented on the International Confere...) file uploaded by t.vanas - Labels: Featured Type-Docs Labels: Featured Type-Docs Sep 05, 2008 r38 (* tagged the release corresponding to MSc Thesis) committed by t.vanas - * tagged the release corresponding to MSc Thesis * tagged the release corresponding to MSc Thesis Aug 26, 2008 QuickstartGuide Wiki page edited by t.vanas Aug 26, 2008 QuickstartGuide Wiki page edited by t.vanas Aug 20, 2008 r35 (* added TU Delft faculty information to documentation files) committed by t.vanas - * added TU Delft faculty information to documentation files * added TU Delft faculty information to documentation files Aug 20, 2008 r34 (* added TU Delft faculty information) committed by t.vanas - * added TU Delft faculty information * added TU Delft faculty information Aug 20, 2008 r33 (* removed redundant signals * changed some signal names acco...) committed by t.vanas - * removed redundant signals * changed some signal names according to documentation * removed redundant signals * changed some signal names according to documentation Aug 20, 2008 r32 (* removed redundant state transition condition check) committed by t.vanas - * removed redundant state transition condition check * removed redundant state transition condition check Aug 19, 2008 OperationsSemantics Wiki page edited by t.vanas Aug 19, 2008 OperationsSemantics Wiki page edited by t.vanas Aug 19, 2008 OperationsSemantics Wiki page edited by t.vanas Aug 19, 2008 VEXOperationsSemantics Wiki page deleted by t.vanas Aug 19, 2008 r27 (* immediate switch constant values are now corresponding to ...) committed by t.vanas - * immediate switch constant values are now corresponding to documented values (SHORT_IMM and BRANCH_IMM values reversed) * immediate switch constant values are now corresponding to documented values (SHORT_IMM and BRANCH_IMM values reversed) Aug 19, 2008 OperationsSemantics Wiki page added by t.vanas Aug 19, 2008 VEXOperationsSemantics Wiki page added by t.vanas Aug 19, 2008 quickstart Wiki page deleted by t.vanas Aug 19, 2008 QuickstartGuide Wiki page added by t.vanas Aug 19, 2008 issue 9 (Pipeline the implementation) reported by t.vanas - From my MSc thesis: --- r-VEX is designed to be easily pipelined, as can be seen from the various stage diagrams with the signal flows. However, the current prototype is not yet pipelined. To have a pipelined implementation, these things have to be done: * Pass destination GR and BR addresses through the execute stage to the writeback stage with pipeline registers, instead of directly driving these addresses from the decode stage to the corresponding register files. * Pass the 'target_' signal bundle through the execute stage to the writeback stage with pipeline registers, instead of bypassing it. * Let consecutive stages only be dependent on control signals drive by their direct neighbour stages, instead of skipping stages. * The 'stop' bit for the fetch stage should be driven by the writeback stage, in order not to lose operations inside the pipeline. * The Program Counter should be updated by the fetch stage upon non-CTRL operations (possible branches). * The current Program Counter value (for the syllables in a certain stage) should be registered between each stage. * When a CTRL syllable is decoded, a signal 'flush_pipeline' should be set, in order to flush the pipeline before branching. From my MSc thesis: --- r-VEX is designed to be easily pipelined, as can be seen from the various stage diagrams with the signal flows. However, the current prototype is not yet pipelined. To have a pipelined implementation, these things have to be done: * Pass destination GR and BR addresses through the execute stage to the writeback stage with pipeline registers, instead of directly driving these addresses from the decode stage to the corresponding register files. * Pass the 'target_' signal bundle through the execute stage to the writeback stage with pipeline registers, instead of bypassing it. * Let consecutive stages only be dependent on control signals drive by their direct neighbour stages, instead of skipping stages. * The 'stop' bit for the fetch stage should be driven by the writeback stage, in order not to lose operations inside the pipeline. * The Program Counter should be updated by the fetch stage upon non-CTRL operations (possible branches). * The current Program Counter value (for the syllables in a certain stage) should be registered between each stage. * When a CTRL syllable is decoded, a signal 'flush_pipeline' should be set, in order to flush the pipeline before branching. Aug 19, 2008 issue 8 (Add branch_taken signal, make waiting_branch state dependent...) Labels changed by t.vanas - Labels: Type-Enhancement −Type-Defect Labels: Type-Enhancement −Type-Defect Aug 19, 2008 issue 8 (Add branch_taken signal, make waiting_branch state dependent...) reported by t.vanas - The transition to the waiting_branch state in the writeback stage should be on a branch_taken signal. At least in the unpipelined implementation. When a branch isn't taken, this saves a cycle. The transition to the waiting_branch state in the writeback stage should be on a branch_taken signal. At least in the unpipelined implementation. When a branch isn't taken, this saves a cycle. Aug 19, 2008 issue 7 (r-ASM: Add support for long immediate operands) reported by t.vanas - Add support for long immediate operands in r-ASM. Issue 6 (r-VEX support for long immediate operands) should be resolved first. Add support for long immediate operands in r-ASM. Issue 6 (r-VEX support for long immediate operands) should be resolved first. Aug 19, 2008 issue 6 (Add support for long immediate operands) reported by t.vanas - Implement support for long immediate operands. There is an immediate switch available for this type of operands. Implement support for long immediate operands. There is an immediate switch available for this type of operands. Aug 19, 2008 issue 5 (r-ASM: Add support for r-OPS configuration file) reported by t.vanas - Add support for r-OPS within a configuration file. A configuration file format has to be determined first. Add support for r-OPS within a configuration file. A configuration file format has to be determined first. Aug 19, 2008 issue 4 (r-ASM: Add support for VEX machine model (.fmm) files) reported by t.vanas - Add support for VEX machine model (.fmm) files to gain 'knowledge' about the target processor. Add support for VEX machine model (.fmm) files to gain 'knowledge' about the target processor. Aug 19, 2008 issue 1 (Logical/select ALU operations fix when BR is destination in ...) Labels changed by t.vanas - Labels: Project-rVEX Labels: Project-rVEX Aug 19, 2008 issue 2 (Add separate link register $l0.0 instead of using $r0.63) Labels changed by t.vanas - Labels: Project-rVEX Labels: Project-rVEX Aug 19, 2008 issue 3 (r-ASM: Add support for hexadecimal immediate notation) Labels changed by t.vanas - Labels: Project-rASM −r-ASM Labels: Project-rASM −r-ASM Aug 19, 2008 issue 3 (r-ASM: Add support for hexadecimal immediate notation) reported by t.vanas - Currently, r-ASM only supports decimal immediate notation. However, the VEX compiler sometimes presents immediate operands as hexadecimal numbers (in 0x<hex> C-like notation). Currently, r-ASM only supports decimal immediate notation. However, the VEX compiler sometimes presents immediate operands as hexadecimal numbers (in 0x<hex> C-like notation). Aug 19, 2008 issue 2 (Add separate link register $l0.0 instead of using $r0.63) reported by t.vanas - Currently, $r0.63 is hardcoded as the link register address. In some VEX documents, $r0.63 is referred for this job, but it seems better to add a dedicated link register to the design. This also avoids issues when less than 64 GR registers are assigned in r-VEX (currently, there is no fix for this case). Currently, $r0.63 is hardcoded as the link register address. In some VEX documents, $r0.63 is referred for this job, but it seems better to add a dedicated link register to the design. This also avoids issues when less than 64 GR registers are assigned in r-VEX (currently, there is no fix for this case). Aug 19, 2008 issue 1 (Logical/select ALU operations fix when BR is destination in ...) reported by t.vanas - On the logical (compare) ALU operations with BR or GR destination register options, no immediate operation is supported when a BR is the destination. This is caused by the fact that part of the immediate field is used by the BR destination address field, as can be see below: 31 23 15 7 0 ^ ^ ^ ^ ^ \| \| \| \| \| \| \| \| \| \|o o o o o o o\|0 0\|d d d d d d\|a a a a a a\|b b b b b b\|k k k\|L\|F\| \| \|S S\| \| \| \| \| \| \| o : Opcode d : Destination register address a : Source register 1 address b : Source register 2 address k : Destination branch register address L : '1' if the syllable is the last in the instruction F : '1' if the syllable is the first in the instruction S S : Immediate switch 0 0 = NO_IMM no immediate value 0 1 = SHORT_IMM short immediate 1 0 = BRANCH_IMM branch offset immediate 1 1 = LONG_IMM long immediate Possible fix: Use SHORT_IMM immediate switch when GR is destination and BRANCH_IMM when BR is target. BR could then be packed in GR destination address field. The BRANCH_IMM switch is normally illegal in ALU operations, so this does not provoke any conflicts. On the logical (compare) ALU operations with BR or GR destination register options, no immediate operation is supported when a BR is the destination. This is caused by the fact that part of the immediate field is used by the BR destination address field, as can be see below: 31 23 15 7 0 ^ ^ ^ ^ ^ \| \| \| \| \| \| \| \| \| \|o o o o o o o\|0 0\|d d d d d d\|a a a a a a\|b b b b b b\|k k k\|L\|F\| \| \|S S\| \| \| \| \| \| \| o : Opcode d : Destination register address a : Source register 1 address b : Source register 2 address k : Destination branch register address L : '1' if the syllable is the last in the instruction F : '1' if the syllable is the first in the instruction S S : Immediate switch 0 0 = NO_IMM no immediate value 0 1 = SHORT_IMM short immediate 1 0 = BRANCH_IMM branch offset immediate 1 1 = LONG_IMM long immediate Possible fix: Use SHORT_IMM immediate switch when GR is destination and BRANCH_IMM when BR is target. BR could then be packed in GR destination address field. The BRANCH_IMM switch is normally illegal in ALU operations, so this does not provoke any conflicts. Aug 18, 2008 quickstart Wiki page edited by t.vanas Aug 18, 2008 quickstart Wiki page edited by t.vanas Aug 18, 2008 quickstart Wiki page edited by t.vanas Aug 18, 2008 quickstart Wiki page edited by t.vanas

issue 9 (Pipeline the implementation) reported by t.vanas - From my MSc thesis: --- r-VEX is designed to be easily pipelined, as can be seen from the various stage diagrams with the signal flows. However, the current prototype is not yet pipelined. To have a pipelined implementation, these things have to be done: * Pass destination GR and BR addresses through the execute stage to the writeback stage with pipeline registers, instead of directly driving these addresses from the decode stage to the corresponding register files. * Pass the 'target_' signal bundle through the execute stage to the writeback stage with pipeline registers, instead of bypassing it. * Let consecutive stages only be dependent on control signals drive by their direct neighbour stages, instead of skipping stages. * The 'stop' bit for the fetch stage should be driven by the writeback stage, in order not to lose operations inside the pipeline. * The Program Counter should be updated by the fetch stage upon non-CTRL operations (possible branches). * The current Program Counter value (for the syllables in a certain stage) should be registered between each stage. * When a CTRL syllable is decoded, a signal 'flush_pipeline' should be set, in order to flush the pipeline before branching.

From my MSc thesis: --- r-VEX is designed to be easily pipelined, as can be seen from the various stage diagrams with the signal flows. However, the current prototype is not yet pipelined. To have a pipelined implementation, these things have to be done: * Pass destination GR and BR addresses through the execute stage to the writeback stage with pipeline registers, instead of directly driving these addresses from the decode stage to the corresponding register files. * Pass the 'target_' signal bundle through the execute stage to the writeback stage with pipeline registers, instead of bypassing it. * Let consecutive stages only be dependent on control signals drive by their direct neighbour stages, instead of skipping stages. * The 'stop' bit for the fetch stage should be driven by the writeback stage, in order not to lose operations inside the pipeline. * The Program Counter should be updated by the fetch stage upon non-CTRL operations (possible branches). * The current Program Counter value (for the syllables in a certain stage) should be registered between each stage. * When a CTRL syllable is decoded, a signal 'flush_pipeline' should be set, in order to flush the pipeline before branching.

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