Introduction

There are 16 basic instructions and 1 advanced call instruction. The design has 4 main registrs to understand. Internally hidden registers are not included in this decription. The registers are labelled P Q R and S, and some auxillary registers are IR (the instruction register) and A (accumulator).

Instruction semantics refer to these registers, by RTL decriptions. P is special, being the program counter. All execution on reset starts from address 0. All indirect register access is pre-decrement store and post-increment fetch.

The lack of full packing in the machine word allows narrow memory to be used in cost efficient situations, while it places no limit on the machine word size at the instruction level, as any useful system will have more than 16 memory locations.

This is an improvement over previous designs in code density, while maintaining reasonable execution efficiency for the density. Mainly because of direct support for threaded code, a compact program representation. The efficiency would drop radically if a non-threaded compilier was used, as most instructions have many high order bits, outside the lowest nibble, set to 0, performing no work. If you are looking for a chip for monolith code you are in the wrong place. The page InstructionExplination covers the meaning of the following list of instructions. Threaded code is the best model for this design.

Details

• Advanced Call IR->P->(R) - Advanced call (has no opcode)

• BA (R)->P - Back (followed by local InterruptMethod vector if IRQ_I used)
• FI (Q)->A - Fetch in
• RI (R)->Q - Return in
• SI (S)->A - Stack in

• DI (S) XOR A->A - Difference (ex-or)
• FA (S)->Q - Fetch Address
• RA (S)->R - Return Address
• SA (S)->S - Stack Address

• BO ((S) AND A) mul 2->A - BOth (CarryRollBit as LSB)
• FO A->(Q) - Fetch Out
• RO Q->(R) - Return Out
• SO A->(S) - Stack Out

• SU (S)+A->A - SUm (CarryRollBit added too)
• FE Q->(S) - Fetch Ends
• RE R->(S) - Return Ends (Also does some special IO)
• SE S->(S) - Stack Ends

This instruction set is Turing complete, and has a 1 memory access per instruction execution model. All 4 main registers are set to 0 on reset.

The use of the CarryRollBit and SU is the main way of branching via indirecting from a subroutine (R). This simplifies the instruction set considerably. Literal fetch can be done by the subroutine RI FI SO RO BA. The literal value follows the call address in the code.