Introduction

This module is designed to decode HSYNC/VSYNC signals and produce a more user friendly set of signals for use with the rest of the design.

Inputs

• CLK - Pixel Clock
• RST - Synchronous active high reset, returns values to the state they would be in after the neg-edge of the VSYNC
• VSYNC - The vertical sync signal
• HSYNC - The horizontal sync signal

Constants

• HEIGHT - The number of rows in the image
• WIDTH - The number of columns in the image
• H_BP - The horizontal back porch. This is the number of pixel clock times between (i.e., not including) the negative edge of the HSYNC and the valid data.
• V_BP - Same idea as H_BP but for the VSYNC. The main difference is this uses the number of HSYNCs whereas the H_BP uses pixel clock times. This is the number of HSYNCs between the negative edge of the VSYNC and the first HSYNC that precedes valid data.
• WIDTH_BITS - The number of bits used to count the pixel clock times between HSYNC negative and positive edges. This includes active pixels, horizontal front porch, and horizontal back porch clock times. (Note, this is always at least the width of the image, but normally more).
• HEIGHT_BITS - The number of bits used to count the HSYNCS between VSYNC negative and positive edges. This includes active pixel, horizontal front porch, and horizontal back porch HSYNCs. (Note, this is always at least the height of the image, but normally more).
• DATA_DELAY - This is used to compensate for a delay in processing the outputs of this module to where the pixel data is eventually used. DATA_DELAY=0 will produce the expected behavior with no delay, DATA_DELAY=1 will start the user signals 1 CT sooner than normal, thus accounting for an external signal delay of 1 CT. For example, if we need to take the pixel count of this module, do some processing on it to produce a memory address for a RAM chip, all of that processing is going to add delays (in CT's) to our video system, thus requiring the data to be buffered in a FIFO so that it can be retrieved when the address is ready to be passed to the RAM, this process can use up a lot of registers and the number of registers has to change whenever the delay changes. Using this setup, all that would need to be changed is the DATA_DELAY parameter and any delay less than the H_BP can be corrected for, thus the control signals and address are ready when the data is, no buffering required.

Outputs

• X_COORD - If the DATA_VALID signal is high, then this represents the x coordinate of the data [0,WIDTH-1].
• Y_COORD - If the DATA_VALID signal is high, then this represents the y coordinate of the data [0,HEIGHT-1].
• PIXEL_COUNT - If the DATA_VALID signal is high, then this represents the 1D coordinate of the data. (i.e., PIXEL_COUNT=X_COORD+WIDTH*Y_COORD) [0,WIDTH*HEIGHT-1].
• DATA_VALID - High when the data corresponding to the HSYNC/VSYNC signals is valid based on the provided constants.

Reset Behavior

When reset is high, the registers are set as if the negative edge of the VSYNC just occurred.

Maximum Transient Time

After startup, the output may be erroneous until the negative edge of the VSYNC occurs.

Notable Assumptions

Details

Timing Diagram