CPU Modes
CPU mode is exposed on psw lines bits [15:14], but cannot be seen by software.
| psw[15:14] | |
| 1 1 | User Mode |
| 0 0 | Kernel Mode |
psw bits [13:12] contain previous mode. In the current arrangement, previous mode is always a user mode because only a kernel mode command MFPI makes use of this. MPFI is fully functional and can be used to retrieve usermode memory and uSP.
CPU has a copy of SP for each mode: uSP and kSP. All other registers are shared.
CPU starts in Kernel mode. The startup code must set up memory mapping, request switch to User mode by setting appropriate bit in MMUCTL register and relay control with an RTI instruction.
Re-entering kernel mode is possible when usermode CPU line is held low during interrupt acknowledgement cycle (IAKO is high), or when a software interrupt is being executed.
The Kernel-key is ScrollLock and it is used to invoke the BIN loader. Kernel mode entry through a software interrupt is used by the EMT36 hook.
Memory Management Control Register (MMUCTL)
177700 Only accessible in kernel mode (0)
| 15 | .. | 3 | 2 | 1 | 0 |
| | | current_cpumode | cpumode_req | mmu_enabled | shadow mode |
- current_cpumode must always read as 0 since this register is only accessible in K-mode
- cpumode_req to switch to usermode, set this bit to "1" and execute RTI/RTT
- mmu_enabled 0: mapping disabled, lower 64K of physical memory are used; 1: mapping enabled
- shadow_mode 1: bootrom is plugged at physical address 0100000 (initial); 0: bootrom is unplugged
Attempting access to this register in user mode will trap through location 4.
Memory Management Registers
177600 - 177616 KISA0-7
and
177620 - 177636 UISA0-7
Only accessible in kernel mode (0)
The MMU contains 2 sets of 8 PAR registers: KISA0-KISA7 for kernel instruction space and UISA0-UISA7 for user instruction space. The physical address is formed from virtual address vadr in the following way:
- bits 15:13 of vadr select corresponding KISA or UISA register, PAR
- physical address = {PAR[14:0] + vadr[12:6], vadr[5:0]}
- page access mode = PAR[15] (1 = RW, 0 = RO)
Physical address can thus have up to 21 lines, but only 18 are currently used. Pages can't have variable sizes. But they can start anywhere in RAM, with 64-byte granularity.
| Kernel | Address | Name | Virtual page | | User | Address | Name | Virtual page | Normal value |
| | 177600 | KISA0 | 000000 | | | 177620 | UISA0 | 000000 | 100000 |
| | 177602 | KISA1 | 020000 | | | 177622 | UISA1 | 020000 | 100200 |
| | 177604 | KISA2 | 040000 | | | 177624 | UISA2 | 040000 | 100400 |
| | 177606 | KISA3 | 060000 | | | 177626 | UISA3 | 060000 | 100600 |
| | 177610 | KISA4 | 100000 | | | 177630 | UISA4 | 100000 | 001000 |
| | 177612 | KISA5 | 120000 | | | 177632 | UISA5 | 120000 | 001200 |
| | 177614 | KISA6 | 140000 | | | 177634 | UISA6 | 140000 | 001400 |
| | 177616 | KISA7 | 160000 | | | 177636 | UISA7 | 160000 | 001600 |
Attempting access to any of the above registers in user mode will trap through location 4.
System memory usage
The system starts up in kernel mode, with mapping disabled and shadow ROM enabled. It is the job of the bootrom to initialize memory mapping, relocate itself to virtual address 01000, disable shadow and relay control to the regular ROM.
User mode 64K are mapped linearly to the lowest 64K of physical RAM. Pages that correspond to addresses 100000 and up are tagged as readonly.
Kernel memory map:
| Virtual | Physical | Description |
| 000000 - 037777 | 200000 - 237777 | BIN loader/EMT36 |
| 040000 - 077777 | 040000 - 077777 | Frame buffer |
| 100000 - 117777 | 100000 - 117777 | BK-0010 BIOS |
| 120000 - 157777 | 000000 - 037777
040000 - 077777 | BIN loader destination |
| | 240000 - 257777 | Frame buffer save area |
| 160000 - 177600 | ... | Unused |
Frame buffer hardware bypasses memory mapper and always uses physical addresses 040000-077777.