Team Members

	Garrett Thomas	Greg Bray	Jeffrey Gorton	Jonathan Morgan	Kyle Stewart
Role:	Quality Assurance	Project Lead	Documentation Lead	Data Analyst	Tech Lead
E-Mail:	garrettthomas125(a)gmail.com	greg.bray(a)gmail.com	jgorton78(a)gmail.com	adamsdaddy(a)gmail.com	kstewart83(a)gmail.com

Note: Original team as dissolved as of Summer 2008. If you have any questions please contact Greg Bray or the faculty advisor Ken Stevens kstevens(a)ece.utah.edu

Project Overview

To build a low cost and simple platform capable of testing NAND flash memory and measuring the failure behavior under different usage patterns.

Project Objectives

Build a simple, flexible, bench top platform for SLC NAND endurance cycle-life testing

Create separate modular functions that can:

Erase
Check for erase failure flag (via Read Status Command)
Verify an erase status failure by reading the failing block and checking for all 0’s
Program Page
Verify programming was successful (via Read Status Command)
Read Page (discard what is read- for read disturb cycling)
Read Verify - compare/verify a block against originally programmed pattern

The user should be able to input (via script, GUI, etc) the set of commands necessary to configure the test environment to perform any sequence of the above functions

User to specify the range of blocks of the device which are to be tested

User to specify the number of cycles that each function is to be repeated

User to select auto-generated random seed data, or be allowed to input a single pattern for device testing

Collect stats on failures and cycle counts

Project Links

Project Proposal

2008 ECE Open House Presentation

IEEE Contest Paper

Weekly Meeting Logs

Source Code Repository

Souce Code Overview

2008 Flash Memory Summit slides