| Projects on Google Code | Results 1 - 9 of 9 |
= Open Source IC Layout Editor =
This is a ground zero for the project in terms of source code development, documentation and bug tracking. The latest release packets, code snapshots, as well as current development activities and issues shall be found here.
=== The goal ===
A fast and reliable ...
VHBP is a floorplanning tool, which can help you with the block placement. This is my master thesis project. FEE, Czech Technical University in Prague.
vlsi,
floorplan,
floorplanning,
placer,
vh,
master,
thesis,
cvut,
fel,
ctu,
fei,
genetic,
algorithm,
poems,
vhbp
My bachelor thesis project. FEE, Czech Technical University in Prague.
vlsi,
floorplan,
genetic,
bachelor,
fel,
ctu,
čvut,
poems,
optimisation,
optimization,
floorplanning,
rectangle,
packing,
solver,
optimiser
This is a source control and issues site of our project.
Class Projects for Pr. Vemuri's VLSI Design Automation course at the University of Cincinnati
*MetaHDL* is a domain-specific language dedicated for _Hardware Description_ in reusable [RTL] designs. It is designed _by RTL coder for RTL coders_, so it is extremely expressive, convenient and efficient for RTL coding. A compiler named `mhdlc` translates MetaHDL source to SystemVerilog which is a...
This is an implementation of a pipeline central processing unit, made in VHDL for the purposes of the VLSI computer systems course at the Faculty of Electrical Engineering, Belgrade.
In this project we implement a software package for operations on layout and GUI. The package realizes manipulations on layout database and the GUI realizes visualization of the package capabilities. The package and the GUI is independent for possibility of standalone usage of the package.
Harvey Mudd College and The University of Adelaide, Australia
A project to create a MIPS microprocessor from Verilog simulation to chip fabrication.