| Projects on Google Code | Results 1 - 10 of 83 |
http://nibz.googlecode.com/files/kring.jpg
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NIBZ is a compact innovative microprocessor desc...
VHDL,
Microprocessor,
FPGA,
CPLD,
FORTH,
Machine,
Instruction,
Tiny,
Small,
Chip,
Layout,
Simple,
Narrow,
Memory,
Design
O Processador Pocket-MIPS Monociclo (PMM) é um processador totalmente baseado na máquina MIPS com implementaç˜ao da via de dados monociclo. As instruç˜oes do PMM possuem apenas 1 byte, o ISA é composto por 10 instruções, há quatro registrados de
propósito geral visíveis aos usuários (0..3)e cada re...
|| http://quicklook.altervista.org/stuff/cpufront.png || Welcome to *GLE-MiPS* || http://quicklook.altervista.org/stuff/cpufront.png ||
This site features a collection of different kind of processors, described in pure vhdl code. All started with a MIPS-like non pipelined cpu from which several b...
vhdl,
mips,
pipeline,
stage,
operation,
hardware,
cpu,
integer,
arithmetic,
logic,
unit,
execution,
alu,
fetch,
instruction
=Projects=
|| *Name* || *Description* || *HW/SW* ||
|| arkanoid || A hardware implementation of the classic paddle board game arkanoid/breakout. || HW ||
|| s3esk_lcd_microblaze_core || An IP core for the 2-line, 16 character display embedded on the Xilinx Spartan-3E Starter Kit || HW + SW ||
...
VHDL,
FPGA,
Spartan-3E,
Xilinx,
arkanoid,
breakout,
UART,
hardware,
electronics,
Microblaze,
C,
Spartan,
sudoku,
solver,
PHP
This project's goal is to have students design and implement an Ethernet switch using Altera's Cyclone II. This is an educational project, and is part of ECE 251: Advanced Digital System Design at Duke University's Pratt School of Engineering.
This is a project for Duke ECE 251 Course.
A student annual hardware project written in vhdl.
15-06-2009
Project has been finished and is available to download from /trunk repository.
(soon in package).
ASU Capstone FPGA design for BASH Robotics
It's my first project in google code。I try to design a microcode machine，which is used to support many intruction set。
This VHDL assembler will be optimized to make the most of the VHDL pipelining in order to produce a perfect program.