Proyecto de curso. Entrega 2.

This is an implementation of a pipeline central processing unit, made in VHDL for the purposes of the VLSI computer systems course at the Faculty of Electrical Engineering, Belgrade.

Its a our first(and last, for god's sake!) cpu in vhdl version. -- b0d supertramp n1p0 supertramp

z80 cpu core emulator

计算机系统结构大实验

CPU design

CPU Doc

More info about this project and VHDL/Verilog tutorials (http://www.tutoriaisengenharia.com) This project is about the porting to FPGA of the Bill's Magic-1 computer (http://www.homebrewcpu.com/) Some Bill's M1 photos: [http://i219.photobucket.com/albums/cc244/leonardoaraujo/PainelMagic1.jpg...

The Z OpenCL Environment = Main Component = * OpenCL compiler * I have implemented a not-completed OpenCL compiler frontend. Although this frontend is not finished, it contains a preprocessor (based on tcc), and a hand-crafted recursive descent parser. * I have implemented a b...

Proof of concept project required by the "Computer architecture and design 2" course at the Faculty of Electrical Engineering, University of Belgrade. It's a complete and fully functional simulator for a CPU of certain architecture and design.