=Introduction= Vtags is an auxiliary tool for verilog coder. It can analyze verilog source code files, and do following two things: #1. create hierarchical report, which figures out the module instantiation tree. #2. create tags, which can be used vi VI eidtor. Yes, just like ctags, but with ...

This project involved the design and development of an open source GPS receiver on an FPGA. The receiver was developed in such a way as to be completely customizable, allowing a user to easily reconfigure it for most applications involving currently-available civilian GPS technology. In addition, th...

Várias aplicações utilizam números reais para o processamento de informação na execução ou simulação de modelos reais e abstratos. Como exemplo, podemos citar os modelos matemáticos para previsão de tempo, simulação de circuitos elétricos e problemas de dinâmica de aeronaves. Processadores modernos,...

Hatch is open source, extensible, and aimed at IC and FPGA designers. Hatch uses a high level register interface description in Python to generate RTL (Verilog), XML, and various documentation formats including HTML and LaTex. This allows the documentation source code and register RTL to exist i...

This is the final project of a Digital Design class. It is aimed to excercise different frequencies and amplitudes on a Spartan FPGA using: -Verilog HDL -Icarus Verilog simulator -Modelsim simulator -Xilinx ISE sinthetizer The documentation can be found here: http://docs.google.com/Doc?id...

这个设计因为我的毕业设计而来，我希望可以通过这个项目，学习到关于CPU设计的一些东西，并且可以用在SOPC中，目标是要好用、简单、高效、省资源！

This project is a simple library extension for Icarus Verilog. It allows for graphical debugging, and is very useful for the development of Verilog based graphic processors.

MIPS/DLX processor in verilog. Student project.

Automatically hook up the Verilog RTL

1. parser for four state vcd file 2. in C++ 3. under Linux platform, ubuntu 8.04 4. compilable by gcc-4.2